The present invention relates generally to correction of integral nonlinearity (INL) errors in SAR ADCs (successive approximation register analog to digital converters), particularly to INL errors caused by voltage coefficients of capacitors therein, and more particularly to improvements which avoid the need to use a complex math engine or computational circuitry to perform the INL corrections.
A SAR (successive approximation register) ADC (analog to digital converter) transforms an analog signal into a digital representation thereof by means of a binary algorithm which performs binary bit-by-bit comparisons after an input voltage is sampled onto a CDAC (capacitor digital to analog converter). This sampling stores charge in the CDAC that is manipulated and compared with a reference to determine a digital output code that most closely represents the analog input voltage.
Capacitors inherently have second order voltage coefficients that cause the amount of charge stored on a capacitor to be non-linear with respect to the voltage across the capacitor. Such voltage coefficients cause INL errors in the output of the ADC. As the analog input voltage being sampled in the ADC increases, the INL error due to the second order coefficient of the CDAC capacitors increases. Differences between an actual SAR ADC transfer curve and an “ideal” straight-line staircase transfer function caused by capacitor voltage coefficients are considered to be INL errors.
The magnitude of INL error in an ADC increases as the magnitude of the input signal increases. This increase in INL error is a result of the characteristic second order or “square law” relationship between the INL error due to the capacitor voltage coefficients of the CDAC capacitors and the voltage across them. Consequently, a doubling of the input voltage range will result in a quadrupled INL error. For example, if a 5 volt peak-to-peak input signal is applied to the SAR ADC and this results in generation of an INL error of 1 LSB, then a 10 volt peak-to-peak input signal would create an error of 4 LSBs at the input signal peak. The center point of a graph of the INL error may shift to either the left or right, based on the matching of the individual capacitors in the CDAC, and also based on whether or not the inputs are unipolar or bipolar (and also inherently based on the voltage coefficients since they are part of the cause of the INL error). The characteristic S-shape of the INL curve of a SAR ADC may be inverted, depending on the algorithm used for converting the input signal.
The closest prior art is believed to include commonly owned U.S. Pat. No. 7,501,965 entitled “Correcting for Errors that Cause Generated Digital Codes to Deviate from Expected Values in an ADC”, issued Mar. 10, 2009 to S. Janakiraman, and also U.S. Pat. No. 7,196,645 entitled “Method and Compensation Device for Compensation of Characteristic Errors of an Analog-Digital Converter” issued Mar. 27, 2007 to Christian Bock.
Prior Art FIG. 1 herein is a copy of FIG. 6 of the '965 patent, which discloses a basic INL correction technique. Prior Art FIG. 2 herein is a copy of FIG. 7 of the '965 patent and discloses details of the CDAC 630 in Prior Art FIG. 1. Comparator 610 compares an intermediate signal (which is produced by CDAC 630 in response to VIN and auxiliary DAC 640) with a mid-level reference voltage to generate an input to SAR logic 626. Auxiliary DAC 640 receives a digital INL error signal computed by error computation block 625 and generates an analog representation of the INL error signal as an input to CDAC 630. The analog representation of the INL error signal is used to correct the analog output voltage produced by CDAC 630. SAR logic 626 performs a typical SAR algorithm to control computation block 625 and CDAC 630. The technique of the '965 patent uses the first few SAR ADC bit decisions of a conversion operation determine the part of the SAR ADC transfer function at which the present conversion process is occurring. Thus, the typical error caused by capacitive voltage coefficients of the CDAC capacitors is corrected before the SAR ADC conversion is finished.
The INL error correction performed in error computation block 625 of the '965 patent is performed by a complex “math engine” which computes various coefficients that are required to determine the INL error corrections in accordance with the complex process and associated equations described therein, and thereby provides a very precise correction for each individual SAR ADC chip. However, the use of the math engine results in the disclosed SAR ADC being undesirably complex, slow, and costly.
In some known CDACs, “dynamic error correction capacitors” are provided to correct for dynamic errors caused by signal voltage settling problems.
Thus, there is an unmet need for a way of inexpensively achieving fast correction of INL errors caused by capacitor voltage coefficients in a SAR ADC.
There also is an unmet need for a SAR ADC which avoids use of a complex mathematics engine to compute various coefficients to use for correction of INL errors during SAR ADC conversion processes.
There also is an unmet need for a simpler, faster way of achieving correction of INL errors due to voltage coefficients in a CDAC of a SAR ADC than is available in the prior art.